The present invention relates to apparatus and methods for processing substrates such as semiconductor substrates for use in IC fabrication or glass panels for use in flat panel display applications. More particularly, the present invention relates to improved techniques for reducing He backside faults during wafer processing.
FIG. 1A illustrates a typical processing module 100 for processing a wafer 112. The processing module 100 generally includes a chamber 114 within which processing takes place, and a chuck 116 for holding the wafer 112 during processing. The processing module 100 also includes a gas inlet port 118 for releasing gaseous source materials, i.e., etchants, into the chamber 114, and a gas exhaust port 120 for exhausting by-product gases formed during processing. The exhaust port 120 is typically coupled to a pump (not shown) that maintains the appropriate pressure inside chamber 114.
The chuck 116 also includes a heat transfer system 122 for controlling the temperature (e.g., cooling) of the wafer 112 during processing. As shown, the heat transfer system 122 is generally configured for distributing He gas to a backside 113 of the wafer 112. In most cases, the heat transfer system 122 includes a mass flow controller 124, a main channel 126, and a plurality of outlet channels 128. The mass flow controller 124 delivers He gas (under pressure) to the main channel 126 and the main channel 126 distributes the He gas to the plurality of outlet channels 128, which then distributes the He gas to the backside 113 of the wafer 112. The He gas then exits out the side of the chuck 116 (as shown by arrow 129) where it is exhausted through exhaust port 120. As should be appreciated, the He gas acts as a heat transfer medium for accurately controlling the temperature of the wafer 112 during processing so as to ensure uniform and repeatable processing results.
A pressure sensor 132 and a controller 134 is also provided to continuously monitor the pressure of the He gas, and adjust the mass flow controller 124 accordingly. For example, the controller 134, via a measurement signal from the pressure sensor 132, generally sends a command signal to the mass flow controller 124 to adjust the He flow so as to maintain a set point pressure at the backside of the wafer 112. In most cases, the set point pressure is maintained throughout a processing task, however, in some cases an He backside fault may be formed when the pressure is too low and/or the flow rate is too high (e.g., base on predetermined limits). By way of example, an He backside fault may occur when an excessive amount of He gas flows out the side of the chuck 116. The He backside fault is typically formed to stop processing so as to prevent undesirable and/or unpredictable gas pressures and gas chemistries from forming in the chamber 114. As should be appreciated, undesirable and/or unpredictable gas pressures and gas chemistries may lead to process drift and/or process failure.
He backside faults, which are caused by excessive He flow, generally occur when the backside of the wafer does not seat properly on the top surface of the chuck, i.e., the backside of the wafer is offset or de-chucked relative to the top surface of the chuck. By way of example, a gap may be formed between the wafer backside and the chuck top surface allowing a greater amount of He gas to escape. As should be appreciated, the escaping gas tends to cause the pressure to decrease and thus the mass flow controller (via the pressure sensor and controller) increases the flow rate of the outputted He gas. It has generally been found that gaps are formed when the wafer is warped or when particles are trapped between the chuck and the wafer. With regards to trapped particles, the particles may be dust, polymer deposits and/or excess photo-resist that has accumulated or collected on the backside of the wafer and/or top surface of the chuck during prior processing steps and/or transfers.
To facilitate discussion, FIG. 1B illustrates the processing module 100 with a gap 136 formed between the bottom side 113 of the wafer 112 and the top surface 117 of the chuck 116. By way of example, the gap 136 may be formed when a particle 138 is trapped between the bottom side 113 of the wafer 112 and the top surface 117 of the chuck 116. As shown, the particle 138 does not allow the wafer 112 to sit flat. In most cases, the gap 136 tends to cause the He gas to escape more readily thus creating excessive He flow (shown by the larger arrow 139). As should be appreciated, the excessive He flow tends to trigger He backside faults.
Conventional methods for overcoming the He backside faults have included clearing the alarm and resuming processing, removing the wafer from the processing module and reprocessing it in the same module at a later time, removing the wafer from the processing module and reprocessing it in a different module at a later time, and/or removing the wafer from the processing module and determining what is causing the error, i.e., polymer deposits, warp, dust, etc. In the later method, if it is determined that dust was the culprit, then the wafer may be cleaned in a water based solution and reprocessed in the same or a different module. If it is determined that photo-resist or polymer deposits are the culprit, then the entire wafer may be stripped in a solvent solution and re-patterned before reprocessing it in the same or a different module.
Unfortunately, however, He backside faults, as well as the aforementioned methods, stop the processing module from continuously running and thus a significant amount of tool downtime may be created. As should be appreciated, downtime leads to a loss in productivity and thus increased costs. For example, the He backside faults may prevent an entire wafer lot from completing that particular processing step and steps that may occur thereafter. By way of example, it may take an operator about 0.25 hours to about 1 hour to clear an He backside fault alarm. In addition, it may take an operator about 0.25 hours to about 2 hours to resume processing or to remove the wafer from the processing module. Further, it may take about 0.5 hours to about 48 hours to make determination of the problem, clean the wafer, re-pattern the wafer and/or reprocess the wafer.
In view of the foregoing, there are desired improved techniques for reducing He backside faults during wafer processing.